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branch-misses
Created: 2025-01-16 05:06:47
Modified: 2025-01-16 05:06:47
bus-cycles
Created: 2025-01-16 05:06:47
Modified: 2025-01-16 05:06:47
tx-commit
Created: 2025-01-16 05:06:47
Modified: 2025-01-16 05:06:47
instructions
Created: 2025-01-16 05:06:47
Modified: 2025-01-16 05:06:47
cycles-t
Created: 2025-01-16 05:06:47
Modified: 2025-01-16 05:06:47
cycles-ct
Created: 2025-01-16 05:06:47
Modified: 2025-01-16 05:06:47
branch-instructions
Created: 2025-01-16 05:06:47
Modified: 2025-01-16 05:06:47
mem-stores
Created: 2025-01-16 05:06:47
Modified: 2025-01-16 05:06:47
cache-misses
Created: 2025-01-16 05:06:47
Modified: 2025-01-16 05:06:47
ref-cycles
Created: 2025-01-16 05:06:47
Modified: 2025-01-16 05:06:47
el-start
Created: 2025-01-16 05:06:47
Modified: 2025-01-16 05:06:47
mem-loads
Created: 2025-01-16 05:06:47
Modified: 2025-01-16 05:06:47
el-abort
Created: 2025-01-16 05:06:47
Modified: 2025-01-16 05:06:47
cache-references
Created: 2025-01-16 05:06:47
Modified: 2025-01-16 05:06:47
el-conflict
Created: 2025-01-16 05:06:47
Modified: 2025-01-16 05:06:47
el-capacity
Created: 2025-01-16 05:06:47
Modified: 2025-01-16 05:06:47
tx-conflict
Created: 2025-01-16 05:06:47
Modified: 2025-01-16 05:06:47
tx-capacity
Created: 2025-01-16 05:06:47
Modified: 2025-01-16 05:06:47
tx-start
Created: 2025-01-16 05:06:47
Modified: 2025-01-16 05:06:47
tx-abort
Created: 2025-01-16 05:06:47
Modified: 2025-01-16 05:06:47
el-commit
Created: 2025-01-16 05:06:47
Modified: 2025-01-16 05:06:47
cpu-cycles
Created: 2025-01-16 05:06:47
Modified: 2025-01-16 05:06:47

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