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branch-misses
Created: 2025-06-04 02:54:13
Modified: 2025-06-04 02:54:13
bus-cycles
Created: 2025-06-04 02:54:13
Modified: 2025-06-04 02:54:13
tx-commit
Created: 2025-06-04 02:54:13
Modified: 2025-06-04 02:54:13
instructions
Created: 2025-06-04 02:54:13
Modified: 2025-06-04 02:54:13
cycles-t
Created: 2025-06-04 02:54:13
Modified: 2025-06-04 02:54:13
cycles-ct
Created: 2025-06-04 02:54:13
Modified: 2025-06-04 02:54:13
branch-instructions
Created: 2025-06-04 02:54:13
Modified: 2025-06-04 02:54:13
mem-stores
Created: 2025-06-04 02:54:13
Modified: 2025-06-04 02:54:13
cache-misses
Created: 2025-06-04 02:54:13
Modified: 2025-06-04 02:54:13
ref-cycles
Created: 2025-06-04 02:54:13
Modified: 2025-06-04 02:54:13
el-start
Created: 2025-06-04 02:54:13
Modified: 2025-06-04 02:54:13
mem-loads
Created: 2025-06-04 02:54:13
Modified: 2025-06-04 02:54:13
el-abort
Created: 2025-06-04 02:54:13
Modified: 2025-06-04 02:54:13
cache-references
Created: 2025-06-04 02:54:13
Modified: 2025-06-04 02:54:13
el-conflict
Created: 2025-06-04 02:54:13
Modified: 2025-06-04 02:54:13
el-capacity
Created: 2025-06-04 02:54:13
Modified: 2025-06-04 02:54:13
tx-conflict
Created: 2025-06-04 02:54:13
Modified: 2025-06-04 02:54:13
tx-capacity
Created: 2025-06-04 02:54:13
Modified: 2025-06-04 02:54:13
tx-start
Created: 2025-06-04 02:54:13
Modified: 2025-06-04 02:54:13
tx-abort
Created: 2025-06-04 02:54:13
Modified: 2025-06-04 02:54:13
el-commit
Created: 2025-06-04 02:54:13
Modified: 2025-06-04 02:54:13
cpu-cycles
Created: 2025-06-04 02:54:13
Modified: 2025-06-04 02:54:13

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