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branch-misses
Created: 2025-03-15 02:45:26
Modified: 2025-03-15 02:45:26
bus-cycles
Created: 2025-03-15 02:45:26
Modified: 2025-03-15 02:45:26
tx-commit
Created: 2025-03-15 02:45:26
Modified: 2025-03-15 02:45:26
instructions
Created: 2025-03-15 02:45:26
Modified: 2025-03-15 02:45:26
cycles-t
Created: 2025-03-15 02:45:26
Modified: 2025-03-15 02:45:26
cycles-ct
Created: 2025-03-15 02:45:26
Modified: 2025-03-15 02:45:26
branch-instructions
Created: 2025-03-15 02:45:26
Modified: 2025-03-15 02:45:26
mem-stores
Created: 2025-03-15 02:45:26
Modified: 2025-03-15 02:45:26
cache-misses
Created: 2025-03-15 02:45:26
Modified: 2025-03-15 02:45:26
ref-cycles
Created: 2025-03-15 02:45:26
Modified: 2025-03-15 02:45:26
el-start
Created: 2025-03-15 02:45:26
Modified: 2025-03-15 02:45:26
mem-loads
Created: 2025-03-15 02:45:26
Modified: 2025-03-15 02:45:26
el-abort
Created: 2025-03-15 02:45:26
Modified: 2025-03-15 02:45:26
cache-references
Created: 2025-03-15 02:45:26
Modified: 2025-03-15 02:45:26
el-conflict
Created: 2025-03-15 02:45:26
Modified: 2025-03-15 02:45:26
el-capacity
Created: 2025-03-15 02:45:26
Modified: 2025-03-15 02:45:26
tx-conflict
Created: 2025-03-15 02:45:26
Modified: 2025-03-15 02:45:26
tx-capacity
Created: 2025-03-15 02:45:26
Modified: 2025-03-15 02:45:26
tx-start
Created: 2025-03-15 02:45:26
Modified: 2025-03-15 02:45:26
tx-abort
Created: 2025-03-15 02:45:26
Modified: 2025-03-15 02:45:26
el-commit
Created: 2025-03-15 02:45:26
Modified: 2025-03-15 02:45:26
cpu-cycles
Created: 2025-03-15 02:45:26
Modified: 2025-03-15 02:45:26

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