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branch-misses
Created: 2025-09-15 07:03:31
Modified: 2025-09-15 07:03:31
bus-cycles
Created: 2025-09-15 07:03:31
Modified: 2025-09-15 07:03:31
tx-commit
Created: 2025-09-15 07:03:31
Modified: 2025-09-15 07:03:31
instructions
Created: 2025-09-15 07:03:31
Modified: 2025-09-15 07:03:31
cycles-t
Created: 2025-09-15 07:03:31
Modified: 2025-09-15 07:03:31
cycles-ct
Created: 2025-09-15 07:03:31
Modified: 2025-09-15 07:03:31
branch-instructions
Created: 2025-09-15 07:03:31
Modified: 2025-09-15 07:03:31
mem-stores
Created: 2025-09-15 07:03:31
Modified: 2025-09-15 07:03:31
cache-misses
Created: 2025-09-15 07:03:31
Modified: 2025-09-15 07:03:31
ref-cycles
Created: 2025-09-15 07:03:31
Modified: 2025-09-15 07:03:31
el-start
Created: 2025-09-15 07:03:31
Modified: 2025-09-15 07:03:31
mem-loads
Created: 2025-09-15 07:03:31
Modified: 2025-09-15 07:03:31
el-abort
Created: 2025-09-15 07:03:31
Modified: 2025-09-15 07:03:31
cache-references
Created: 2025-09-15 07:03:31
Modified: 2025-09-15 07:03:31
el-conflict
Created: 2025-09-15 07:03:31
Modified: 2025-09-15 07:03:31
el-capacity
Created: 2025-09-15 07:03:31
Modified: 2025-09-15 07:03:31
tx-conflict
Created: 2025-09-15 07:03:31
Modified: 2025-09-15 07:03:31
tx-capacity
Created: 2025-09-15 07:03:31
Modified: 2025-09-15 07:03:31
tx-start
Created: 2025-09-15 07:03:31
Modified: 2025-09-15 07:03:31
tx-abort
Created: 2025-09-15 07:03:31
Modified: 2025-09-15 07:03:31
el-commit
Created: 2025-09-15 07:03:31
Modified: 2025-09-15 07:03:31
cpu-cycles
Created: 2025-09-15 07:03:31
Modified: 2025-09-15 07:03:31

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