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branch-misses
Created: 2025-02-06 12:35:48
Modified: 2025-02-06 12:35:48
bus-cycles
Created: 2025-02-06 12:35:48
Modified: 2025-02-06 12:35:48
tx-commit
Created: 2025-02-06 12:35:48
Modified: 2025-02-06 12:35:48
instructions
Created: 2025-02-06 12:35:48
Modified: 2025-02-06 12:35:48
cycles-t
Created: 2025-02-06 12:35:48
Modified: 2025-02-06 12:35:48
cycles-ct
Created: 2025-02-06 12:35:48
Modified: 2025-02-06 12:35:48
branch-instructions
Created: 2025-02-06 12:35:48
Modified: 2025-02-06 12:35:48
mem-stores
Created: 2025-02-06 12:35:48
Modified: 2025-02-06 12:35:48
cache-misses
Created: 2025-02-06 12:35:48
Modified: 2025-02-06 12:35:48
ref-cycles
Created: 2025-02-06 12:35:48
Modified: 2025-02-06 12:35:48
el-start
Created: 2025-02-06 12:35:48
Modified: 2025-02-06 12:35:48
mem-loads
Created: 2025-02-06 12:35:48
Modified: 2025-02-06 12:35:48
el-abort
Created: 2025-02-06 12:35:48
Modified: 2025-02-06 12:35:48
cache-references
Created: 2025-02-06 12:35:48
Modified: 2025-02-06 12:35:48
el-conflict
Created: 2025-02-06 12:35:48
Modified: 2025-02-06 12:35:48
el-capacity
Created: 2025-02-06 12:35:48
Modified: 2025-02-06 12:35:48
tx-conflict
Created: 2025-02-06 12:35:48
Modified: 2025-02-06 12:35:48
tx-capacity
Created: 2025-02-06 12:35:48
Modified: 2025-02-06 12:35:48
tx-start
Created: 2025-02-06 12:35:48
Modified: 2025-02-06 12:35:48
tx-abort
Created: 2025-02-06 12:35:48
Modified: 2025-02-06 12:35:48
el-commit
Created: 2025-02-06 12:35:48
Modified: 2025-02-06 12:35:48
cpu-cycles
Created: 2025-02-06 12:35:48
Modified: 2025-02-06 12:35:48